1. Field of the Invention
The present invention generally relates to methods and apparatuses for driving display panels. More specifically, the present invention relates to methods and apparatuses adapted to drive signal lines within display panels in a time divisional manner.
2. Description of the Related Art
Recent display panels are composed of an increased number of signal lines (or data lines) with reduced intervals therebetween; this is a basic requirement for high-resolution display panels. The increase in the number of signal lines and/or the reduction in the intervals thereof, however, undesirably cause a problem in providing electrical connection between the display panel and the display panel driver with external wiring lines. The reduction in the intervals of the signal lines undesirably reduce pitches allowed to the external connecting wiring lines, so that the display panel experiences a difficulty in achieving electrical connection to the display panel driver. Another problem caused by the increase in the number of data lines is an undesirable increase in the number of amplifiers used for driving data lines. The increase in the number of the amplifiers undesirably increases the size and cost of the display panel driver.
Time-divisional driving, which involves driving signal lines within the display panel in a time-divisional manner, is one of the promising techniques for overcoming such problems. Japanese Laid-open Patent Application No. H04-52684, for instance, discloses a liquid crystal display device in which each set of three data lines are switched by a switching circuitry disposed within a liquid crystal display panel for achieving time-divisional driving of each three signal lines.
FIG. 1 is a block diagram for schematically showing the known liquid crystal display device. This liquid crystal display device is designed to drive each set of three signal lines with a single amplifier in a time divisional manner.
Specifically, the conventional liquid crystal display device is provided with a liquid crystal display panel 10 and a driver 20. The liquid crystal display panel 10 is equipped with signal lines “D1” to “D3,”, scan lines (or gate lines) “G1” to “GM”, and pixels “C11” to “CM3”, being a natural number equal to or larger than 2; it should be understood that all of the components within the liquid crystal display panel 10 are not shown for simplicity. The signal lines D1 to D3 are associated with red (R), green (G) and blue (B), respectively. The pixels C11 to CM3 are provided at respective intersections of the signal lines D1 to D3 and the scan lines G1 to GM. Each of the pixels C11 to CM3 is equipped with a TFT (thin-film transistor) 11 and a liquid crystal capacitor 12. The liquid crystal capacitors 12 are each constituted by a set of pixel electrode 12a and a common electrode 12b spaced with liquid crystal material. The TFT 11 within the pixel “Cij” has a source connected to the signal “Di”, a gate connected to the scan line “Gj”, and a drain connected to the pixel electrode 12a of the liquid crystal capacitor 12.
The respective signal lines D1 to D3 are connected with an input terminal 14 through switches 131 to 133. The switches 131 to 133 are each composed of one or more TFTs disposed within the liquid crystal display panel 10. The switches 131 to 133 are turned on and off in response to control signals “S1” to “S3” received from the driver 20. The input terminals 14 receive drive voltages from the driver 20, which are to be applied to the pixels C11 to CM3. It should be noted that the drive voltage to be applied to the pixel “Cij” may be referred to as the drive voltage “Vij” in the following. The switches 131 to 133 are sequentially switched to forward the drive voltages to the desired signal lines D1 to D3.
The driver 20 is provided with a shift register 21, a data register 22, a latch circuit 23, a D/A converter 24, and a set of amplifiers 25. The shift register 21 shifts data bits therethrough in response to an externally inputted clock signal “CLK” so as to produce a set of shift pulses. The data register 22 is designed to latch RGB pixel data representative of grayscale levels of the pixels within the display panel 10, using the shift pulses as triggers. The latch circuit 23 is designed to latch the RGB data from the data register 22, and to forward the latched RGB data to the D/A converter 24. The D/A converter 24 externally receives a set of grayscale voltages, and selects desired ones of the grayscale voltages in response to the forwarded RGB data. The selected grayscale voltages are sequentially supplied to the associated amplifiers 25. The amplifiers 25 develop drive voltages corresponding to the grayscale voltages received from the D/A converter 24 on the associated input terminals 14 of the liquid crystal display panel 10.
The driver 20 is further equipped with a control circuit 26 that produces control signals “S1” to “S3.” The control circuit 26 supplies the control signals S1 to S3 to the switches 131 to 133 to selectively turn on desired one of the switches 131 to 133. The control circuit 26 additionally provides timing control so that the amplifiers 25 develop the drive voltages on the input terminals 14 in synchronization with the timing of the control signals S1 to S3. The on/off timing control of the switches 131 to 133 is important for a desired drive voltage is applied to a desired signal line in synchronization with the development of the drive voltage on the desired input terminal 14. The control circuit 26 executes the above-described timing control in accordance with a program stored in a storage device (not shown) within the driver 20.
Writing the drive voltages “Vn1” to “Vn3” into the pixels “Cn1” to “Cn3”, positioned in the n-th pixel line of the display panel 10, is exemplarily carried out during the n-th horizontal scanning period as follows.
First, the scan line “Gn”, connected to the pixels Cn1 to Cn3 in the n-th pixel line, is activated to turn on the TFTs 11 within the pixels Cn1 to Cn3. This provides electrical connections between the pixels Cn1 to Cn3 and the associated signal lines D1 to D3.
The drive voltages Vn1, associated with the pixels Cn1, are applied from the associated amplifiers 25 to the associated input terminals 14. In synchronization with the input of the drive voltages Vn1, the switches 131 are turned on, while the remaining switches 132 and 133 are turned off. As a result, the signal lines D1 are connected to the associated input terminals 14, and the remaining signal lines D2 and D3 are disconnected from the input terminals 14. The drive voltages Vn1 are applied through the signal lines D1 to the associated pixels Cn1, and are then written into the pixels Cn1. This results in that the drive voltages Vn1 are developed across the associated liquid crystal capacitors within the pixels Cn1).
Subsequently, the drive voltages Vn2 associated with the pixels Cn2 are applied from the amplifier 25 to the input terminal 14. In synchronism with the input of the drive voltages Vn2, the switches 132 are turned on, and the remaining switches 131 and 133 are turned off. As a result, the input terminals 14 are connected to the signal lines D2, and the drive voltages Vn2 are written via the signal lines D2 to the associated pixels Cn2.
Correspondingly, the drive voltages Vn3, associated with the pixels Cn3, are applied from the amplifiers 25 to the associated input terminals 14. In synchronism with the input of the drive voltages Vn3, the switches 133 are turned on, and the remaining switches 131 and 132 are turned off. As a result, the input terminals 14 are connected to the signal lines D3, and the drive voltages Vn3 are written via the signal lines D3 to the associated pixels Cn3.
In accordance with the above-described sequence, each set of the signal lines D1 to D3 are time-divisionally driven by the associated single amplifier 25, so that the drive voltages Vn1 to Vn3 are written into the associated pixels Cn1 to Cn3. Driving the pixels Cn1 to Cn3 are performed in this order of the pixels Cn1, Cn2, and Cn3.
The above-described patent publication also discloses that the signal lines may not be associated with R, G, and B, and the number of signal lines driven by a single amplifier may be two, four, or more. In addition, Japanese Laid-open Patent Application No. 2001-109435 discloses a technique for switching each two signal lines by a selecting circuit within a display panel. Also, Japanese Laid-open patent Application No. 2001-337657 discloses that a set of six signal lines are switched by the six analog switches within a display panel.
One problem of the conventional time-divisional driving technique is that the drive voltages developed across the liquid crystal capacitors 12 may vary from the desirable drive voltages, after the associated signal lines are disconnected from the input terminals 14.
There are three possible causes for the voltage variation across the liquid crystal capacitors 12. The first cause may be that the TFTs within the switches 131 to 133 experience considerable leakage therethrough. Referring now to FIG. 1, the TFTs within the switches 131 to 133 are required to have an increased gate width and a decreased gate length for rapidly driving the signal lines D1 to D3, which have an increased length and increased capacitance. Such designed TFTs, however, often suffer from considerable leakage. The leakage through the switches 131 to 133 provide discharge paths for the charges accumulated on the pixel electrodes 12a within the respective pixels. This results in undesirable variation in the drive voltages across the pixels. The leakage through the switches 131 to 133 may be serious, especially in the case when adjoining signal lines are driven with largely different drive voltages.
The second cause may be related to capacitive couplings between signal lines, as disclosed in the aforementioned Japanese Laid-open Patent Application No. 2001-109435. For example, driving the signal, lines D2 may cause variation in the voltages on the signal lines D1 after the signal lines D1 are placed into the high impedance state, due to the capacitive coupling between the signal lines D1 and D2. The variation in the voltages of the signal lines D1 may cause variation in the drive voltages across the pixels connected to the signal lines D1.
The third cause may be related to variation in the common voltage developed on the common electrode 12b, which is referred to as the common voltage VCOM. The common voltage VCOM is required to be stable during driving the pixels for developing desired drive voltages across the desired pixels; however, the common voltage VCOM may vary due to various reasons, including capacitive couplings between the common electrode 12b and other conductors, and the leakage from the common electrode 12b. The variation in the common voltage VCOM may cause the variation of the drive voltages across the pixels from desired voltages.
Such drive voltage variations are undesirably recognized by human eyes as vertical segments of uneven brightness, extending along the signal lines D1 to D3. The variations in the drive voltages may give undesirable influences to image qualities of the liquid crystal display panel 10.
The increase in the number of the signal lines driven with a single amplifier undesirably enhances the variations of the drive voltages. Therefore, the variations in the drive voltages is one of the major factors which impede commercial use of next-generation liquid crystal display panels designed to time-divisionally drive a set of six signal lines using a single amplifier.
The above-described Japanese Laid-open Patent Application No. 2001-109435 also discloses a display device adapted to drive each pair of signal lines with a single amplifier in which the order of driving the pair of the signal lines is switched every vertical scanning period and/or every horizontal scanning period. This technique is effective for spatially or temporally distributing pixels experiencing the variations of the drive voltages, and thereby eliminating undesirable vertical segments of uneven brightness.